WORM Solution
ECHO CANCEL
WORM row 9

Prerequisites
Unlocks
w44 solved
Walkthrough
ECHO CANCEL: OUT = IN[k]: IN[k-2] (first two outputs pass IN through).
Engine note: a MOV port,port (link->link) DROPS its read value whenever the
write side stalls a cycle, so every relay here is split MOV ACC,port /
MOV port,ACC (ACC holds the value across the stall). No JMPs: each core is a
single loop and the PC wraps from the last line to line 0, saving a cycle/loop.
core 0 read input; fan a live copy DOWN->core4 and a copy RIGHT->core1.
core 1 buffer that copy DOWN->core5 (split relay).
core 5 register-buffered delay-by-2 generator: ACC/BAK shift, emit BAK via
XCH. ACC starts 0, so it emits 0,0,in0,in1,... (the -2 history) LEFT
into core4.
core 4 ACC = live(UP) ; SUB delayed(RIGHT) ; emit DOWN->core8.
core 8 drain to output stream 0.
Rack Solution
# ECHO CANCEL: OUT = IN[k]: IN[k-2] (first two outputs pass IN through).
# Engine note: a MOV port,port (link->link) DROPS its read value whenever the
# write side stalls a cycle, so every relay here is split MOV ACC,port /
# MOV port,ACC (ACC holds the value across the stall). No JMPs: each core is a
# single loop and the PC wraps from the last line to line 0, saving a cycle/loop.
#
# core 0 read input; fan a live copy DOWN->core4 and a copy RIGHT->core1.
# core 1 buffer that copy DOWN->core5 (split relay).
# core 5 register-buffered delay-by-2 generator: ACC/BAK shift, emit BAK via
# XCH. ACC starts 0, so it emits 0,0,in0,in1,... (the -2 history) LEFT
# into core4.
# core 4 ACC = live(UP) ; SUB delayed(RIGHT) ; emit DOWN->core8.
# core 8 drain to output stream 0.
@1
MOV ACC, UP
MOV DOWN, ACC
MOV RIGHT, ACC
@2
MOV ACC, LEFT
MOV DOWN, ACC
@5
XCH
MOV LEFT, ACC
MOV ACC, UP
@4
MOV ACC, UP
SUB RIGHT
MOV DOWN, ACC
@7
MOV DOWN, UP