TWO PHASE WAIT

; TWO PHASE WAIT reference. The CLOCK DIVIDER on p4 toggles every K ticks. The firmware
; makes a non-overlapping two-phase clock: phase A drives CH1 high with CH2 low, then on
; the next hardware edge phase B drives CH2 high with CH1 low. A WAIT on p4 separates
; every phase, so the firmware never counts ticks and the two-phase output stays aligned
; to the divider for any period K and any start phase in the battery.
loop:
        out  p0, 200       ; phase A: CH1 high
        out  p1, 0         ; CH2 held low
        wait p4            ; release on the next clock edge
        out  p0, 0         ; phase B: CH1 low
        out  p1, 150       ; CH2 high
        wait p4            ; release on the following edge
        jmp  loop

# TWO PHASE WAIT. ACT 5. SCOPE waveform board.
# TITLE TWO PHASE WAIT
# OBJECTIVE Generate a non-overlapping two-phase clock locked to the hardware edge.
# A CLOCK DIVIDER toggles p4 every K ticks. The firmware drives two phases that never
# overlap: on one clock half CH1 is high and CH2 is low; on the next half they swap.
# Between every phase the firmware WAITs on the hardware edge, so the two-phase clock
# stays glued to the divider whatever its period or start alignment is. The battery
# moves both the period K and the start phase, so a counted-slp transcript tuned to one
# alignment diverges on the next: only riding the hardware edge locks every case.
ID sc_a5_13_two_phase_wait
WINDOW 96
DIR p0 OUT
DIR p1 OUT
DIR p4 IN
PERIPH CLOCK in=p4 k=8 label=CLOCK_on_p4
CHAN p0 ANALOG label=CH1_p0_phase_A
CHAN p1 ANALOG label=CH2_p1_phase_B
CASE k=8 phase=0
PAR power=80 lines=10 chips=1