THRESHOLD GATE

; THRESHOLD GATE reference. The COMPARATOR on p5 reads HIGH once the ramp on p0
; passes the per-case threshold. The firmware climbs a rising ramp on p0, reads the
; comparator back with inp every tick, and mirrors it as a full-scale gate on p1. The
; firmware never names the threshold: the hardware decides where the gate opens, so
; the same firmware tracks every case in the battery.
        mov  r0, 0         ; r0 = the rising ramp level
loop:
        out  p0, r0        ; drive the ramp on CH1 (the comparator watches this pin)
        inp  r1, p5        ; read the comparator: HIGH once the ramp cleared thr
        out  p1, r1        ; mirror it as the gate on CH2 (0 or 255)
        slp  1
        add  r0, 8         ; climb the ramp one step
        jmp  loop

# THRESHOLD GATE. ACT 3. SCOPE waveform board.
# TITLE THRESHOLD GATE
# OBJECTIVE Open a gate the instant a rising ramp clears the hidden threshold.
# A COMPARATOR watches the ramp the firmware drives on p0 and presents HIGH on p5
# once the level passes a per-case threshold. The firmware climbs the ramp on CH1,
# reads the comparator back with inp, and opens a full-scale gate on CH2 while the
# comparator reads HIGH. The battery moves the threshold, so a transcript with the
# gate hard-wired to one tick diverges on the next: only reading the comparator and
# mirroring it locks every case.
ID sc_a3_11_threshold_gate
WINDOW 64
DIR p0 OUT
DIR p1 OUT
DIR p5 IN
PERIPH DAC data=p0 label=DAC_ramp_p0
PERIPH COMPARATOR data=p0 in=p5 thr=100 label=COMP_p0_gt_thr
CHAN p0 ANALOG label=CH1_p0_ramp
CHAN p1 ANALOG label=CH2_p1_gate
CASE thr=100
PAR power=400 lines=13 chips=2