CLOCK AND LEVEL

; CLOCK AND LEVEL reference. The CLOCK DIVIDER on p4 toggles every K ticks; the
; firmware never counts ticks, it WAITs on the clock edge, so the square on p0 and
; the ladder on p1 stay aligned to the hardware for any K. p0 toggles on every
; edge (half-period K), p1 holds a level that steps one rung per full clock cycle.
        mov  r1, 64        ; r1 is the ladder level on p1
loop:
        out  p0, 255       ; square HIGH for this clock half
        out  p1, r1        ; hold the ladder level
        wait p4            ; release on the next clock edge
        out  p0, 0         ; square LOW for the next half
        out  p1, r1        ; keep holding the ladder
        wait p4            ; release on the following edge (one full cycle done)
        add  r1, 48        ; step the ladder one rung per cycle
        jmp  loop

# CLOCK AND LEVEL. ACT 3. SCOPE waveform board.
# TITLE CLOCK AND LEVEL
# OBJECTIVE Lock a square to the hardware clock while a slow ladder steps each cycle.
# A CLOCK DIVIDER toggles p4 every K ticks; the firmware must WAIT on that edge so
# the square on p0 stays dead steady whatever K is, and the ladder on p1 advances
# one rung per full clock cycle. The battery moves K, so a counted-slp transcript
# tuned to one period diverges on the next; only reading the clock locks all cases.
ID sc_a3_03_clock_and_level
WINDOW 64
DIR p0 OUT
DIR p1 OUT
DIR p4 IN
PERIPH CLOCK in=p4 k=8 label=CLOCK_on_p4
CHAN p0 ANALOG label=CH1_p0_square
CHAN p1 ANALOG label=CH2_p1_ladder
CASE k=8
PAR power=80 lines=11 chips=1