LATCHED ECHO

; LATCHED ECHO reference. The LATCH on p0/p2/p3 captures the live level staged on
; D (p2) when the strobe (p3) is pulsed, and holds it on Q (p0). The firmware climbs
; a live level on p1, stages the same level on D, then strobes once per step, so the
; watched Q replays the previous step while the live line advances. The step height
; is the per-case seed (input[0]), never an immediate, so the echo generalizes.
        mov  r0, 0
        ldb  r4, [r0]      ; r4 = input[0] = per-case step height
        mov  r5, 0         ; r5 = live level
loop:
        out  p1, r5        ; show the live level
        out  p2, r5        ; stage the live level on the latch D
        slp  2             ; hold so the echo and the live line are both visible
        out  p3, 255       ; strobe: capture D into Q (atomic publish)
        slp  1
        out  p3, 0         ; release the strobe (the rising edge captured)
        slp  1
        add  r5, r4        ; advance the live level by the per-case step
        jmp  loop

# LATCHED ECHO. ACT 5. SCOPE waveform board.
# TITLE LATCHED ECHO
# OBJECTIVE Publish each live level into a LATCH so its Q echoes one step behind.
# A real LATCH chip holds the byte on its D pin when STROBE is pulsed and presents
# it on Q; the firmware drives a climbing live level on p1, stages it on the latch
# D, and strobes once per step, so the watched Q on p0 replays the previous level
# while the live line advances. The battery moves the per-case step (seeded into the
# input), so a transcript of one echo diverges on the next: only staging on D and
# pulsing the strobe, then reading the seed, locks every case.
ID sc_a5_09_latched_echo
WINDOW 96
DIR p1 OUT
DIR p2 OUT
DIR p3 OUT
DIR p0 IN
PERIPH DAC data=p1 label=DAC_on_p1
PERIPH LATCH data=p2 strobe=p3 q=p0 label=LATCH_Q_on_p0
CHAN p0 ANALOG label=CH1_p0_latch_Q
CHAN p1 ANALOG label=CH2_p1_live
CASE phase=20
INPUT addr=0 label=STEP
PAR power=420 lines=13 chips=2